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standard eeprom ics slx 24c01/02 1/2 kbit (128/256 8bit) serial cmos-eeprom with i 2 c synchronous 2-wire bus data sheet 1998-07-27
i 2 cbus purchase of siemens i 2 c components conveys the license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. edition 1998-07-27 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1998. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. slx 24c01/02 revision history: current version: 1998-07-27 previous version: 06.97 page (in previous version) page (in current version) subjects (major changes since last revision) 3 3 text was changed to typical programming time 5 ms for up to 8 bytes. 55wp= v cc protects the upper half entire memory. 15 15 figure 11: second command byte is a csr and not csw. 4,5 4,5 cs0,cs1andcs2werereplacedbyn.c. 5 C the paragraph chip select (cs0, cs1, cs2) was removed completely. 11, 12 11, 12 the erase/write cycle is finished latest after 10 8ms. 19 19 capacitive load were added. 20 20 some timings were changed. 20 20 the line erase/write cycle was removed. 20 20 chapter 7.4 erase and write characteristics has been added.
p-dip-8-4 p-dso-8-3 1/2 kbit (128/256 8bit)serialcmos eeproms, i 2 c synchronous 2-wire bus slx 24c01/02 semiconductor group 3 1998-07-27 features ? data eeprom internally organized as 128/256 bytes and 16/32 pages 8bytes ? low power cmos ? v cc = 2.7 to 5.5 v operation ? two wire serial interface bus, i 2 c-bus compatible ? filtered inputs for noise suppression with schmitt trigger ? clock frequency up to 400 khz ? high programming flexibility C internal programming voltage C self timed programming cycle including erase C byte-write and page-write programming, between 1 and 8 bytes C typical programming time 5 ms for up to 8 bytes ? high reliability C endurance 10 6 cycles 1) C data retention 40 years 1) C esd protection 4000 v on all pins ? 8 pin dip/dso packages ? available for extended temperature ranges C industrial: - 40 c to + 85 c C automotive: - 40 c to + 125 c 1) values are temperature dependent, for further information please refer to your siemens sales office.
slx 24c01/02 semiconductor group 4 1998-07-27 ordering information other types are available on request C temperature range (C 55 c ? + 150 c) C package (die, wafer delivery) 1 pin configuration figure 1 pin configuration (top view) type ordering code package temperature voltage sla 24c01-d q67100-h3543 p-dip-8-4 C 40 c + 85 c 4.5 v...5.5 v sla 24c01-s q67100-h3218 p-dso-8-3 C 40 c + 85 c 4.5 v...5.5 v sla 24c01-d-3 q67100-h3217 p-dip-8-4 C 40 c + 85 c 2.7 v...5.5 v sla 24c01-s-3 q67100-h3496 p-dso-8-3 C 40 c + 85 c 2.7 v...5.5 v sle 24c01-d q67100-h3544 p-dip-8-4 C 40c + 125 c 4.5 v...5.5 v sle 24c01-s q67100-h3492 p-dso-8-3 C 40c + 125 c 4.5 v...5.5 v sla 24c02-d q67100-h3539 p-dip-8-4 C 40 c + 85 c 4.5 v...5.5 v sla 24c02-s q67100-h3534 p-dso-8-3 C 40 c + 85 c 4.5 v...5.5 v sla 24c02-d-3 q67100-h3538 p-dip-8-4 C 40 c + 85 c 2.7 v...5.5 v sla 24c02-s-3 q67100-h3533 p-dso-8-3 C 40 c + 85 c 2.7 v...5.5 v sle 24c02-d q67100-h3220 p-dip-8-4 C 40c + 125 c 4.5 v...5.5 v sle 24c02-s q67100-h3221 p-dso-8-3 C 40c + 125 c 4.5 v...5.5 v iep02515 cc v 18 wp v 7 2 scl 6 3 sda 5 4 ss n.c. n.c. n.c. p-dso-8-3 iep02514 n.c. 5 6 7 8 4 3 2 1 v ss wp scl sda cc v n.c. n.c. p-dip-8-4
slx 24c01/02 semiconductor group 5 1998-07-27 pin definitions and functions pin description serial clock (scl) the scl input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge. serial data (sda) sda is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. the output is open drain, performing a wired and function with any number of other open drain or open collector devices. the sda bus requires a pull-up resistor to v cc . write protection (wp) wp switched to v ss allows normal read/write operations. wp switched to v cc protects the entire eeprom against changes (hardware write protection). table 1 pin no. symbol function 1, 2, 3 n.c. not connected 4 v ss ground 5 sda serial bidirectional data bus 6 scl serial clock input 7 wp write protection input 8 v cc supply voltage
slx 24c01/02 semiconductor group 6 1998-07-27 2 description the slx 24c01/02 device is a serial e lectrically e rasable and p rogrammable r ead o nly m emory (eeprom), organized as 128/256 8 bit. the data memory is divided into 16/ 32 pages. the 8 bytes of a page can be programmed simultaneously. the device conforms to the specification of the 2-wire serial i 2 c-bus. low voltage design permits operation down to 2.7 v with low active and standby currents. the device operates at 5.0 v 10% with a maximum clock frequency of 400 khz and at 2.7 ... 4.5 v with a maximum clock frequency of 100 khz. the device is available as 5 v type ( v cc = 4.5 5.5 v) with two temperature ranges for industrial and automotive applications and as 3 v type ( v cc = 2.7 5.5 v) for industrial applications. the eeproms are mounted in eight-pin dip and dso packages or are also supplied as chips. figure 2 block diagram dec x eeprom y dec dout/ack sda scl ieb02530 logic stop start/ control chip address logic h.v. pump programming control control serial logic logic address page logic ss v cc v wp
slx 24c01/02 semiconductor group 7 1998-07-27 3 i 2 c-bus characteristics the slx 24c01/02 devices support a master/slave bidirectional bus oriented protocol in which the eeprom always takes the role of a slave. figure 3 bus configuration master device that initiates the transfer of data and provides the clock for both transmit and receive operations. slave device addressed by the master, capable of receiving and transmitting data. transmitter the device with the sda as output is defined as the transmitter. due to the open drain characteristic of the sda output the device applying a low level wins. receiver the device with the sda as input is defined as the receiver. slave 1 slave 2 slave 3 slave 4 slave 8 slave 5 slave 6 slave 7 master v cc cc v ies02183 scl sda
slx 24c01/02 semiconductor group 8 1998-07-27 the conventions for the serial clock line and the bidirectional data line are shown in figure 4 . figure 4 i 2 c-bus timing conventions for start condition, stop condition, data valida- tion and transfer of acknowledge ack standby mode in which the bus is not busy (no serial transmission, no programming): both clock (scl) and data line (sda) are in high state. the device enters the standby mode after a stop condition or after a programming cycle. start condition high to low transition of sda when scl is high, preceding all commands. stop condition low to high transition of sda when scl is high, terminating all communications. a stop condition initiates an eeprom programming cycle. a stop condition after reading a data byte from the eeprom initiates the standby mode. acknowledge a successful reception of eight data bits is indicated by the receiver by pulling down the sda line during the following clock cycle of scl (ack). the transmitter on the other hand has to release the sda line after the transmission of eight data bits. the eeprom as the receiving device responds with an acknowledge, when addressed. the master, on the other side, acknowledges each data byte transmitted by the eeprom and can at any time end a read operation by releasing the sda line (no ack) followed by a stop condition. data transfer data must change only during low scl state, data remains valid on the sda bus during high scl state. nine clock pulses are required to transfer one data byte, the most significant bit (msb) is transmitted first. 12 8 9 1 9 ack ack start condition data allowed stop condition to change acknowledge scl sda ied02128
slx 24c01/02 semiconductor group 9 1998-07-27 4 device addressing and eeprom addressing after a start condition, the master always transmits a command byte csw or csr. after the acknowledge of the eeprom a control byte follows, its content and the transmitter depend on the previous command byte. the description of the command and control bytes is shown in table 2 . the device has an internal address counter which points to the current eeprom address. the address counter is incremented C after a data byte to be written has been acknowledged, during entry of further data byte C during a byte read, thus the address counter points to the following address after reading a data byte. command byte selects operation: the least significant bit b0 is low for a write operation (c hip s elect w rite command byte csw) or set high for a read operation (c hip s elect r ead command byte csr). in both command bytes, the bit positions b3 to b1 are left undefined. control byte following csw (b0 = 0): contains the seven or eight lower bits of the eeprom address (eea) bit a6 or a7 to a0. following csr (b0 = 1): contains the data read out, transmitted by the eeprom. the eeprom data are read as long as the master pulls down sda after each byte in order to acknowledge the transfer. the read operation is stopped by the master by releasing sda (no acknowledge is applied) followed by a stop condition. table 2 command and control byte for i 2 c-bus addressing of chip and eeprom definition function b7 b6 b5 b4 b3 b2 b1 b0 csw 1010xxx0chipselectforwrite csr 1 0 1 0 x x x 1 chip select for read eea a7 a6 a5 a4 a3 a2 a1 a0 eeprom address
slx 24c01/02 semiconductor group 10 1998-07-27 the timing conventions for read and write operations are described in figures 5 and 6 . figure 5 timing of the command byte csw figure 6 timing of the command byte csr 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 0 1 0 xxx 0 a7 a6 a5 a4 a3 a2 a1 a0 ack start from master acknowledge from eeprom acknowledge from eeprom scl sda command byte (csw) data transfer to eeprom ied02255 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 0 1 0 xxx 1 ack start from master acknowledge from master acknowledge from eeprom scl sda command byte (csr) data transfer from eeprom ied02185 ack
slx 24c01/02 semiconductor group 11 1998-07-27 5 write operations changing of the eeprom data is initiated by the master with the command byte csw. depending on the state of the write protection pin wp either one byte (byte write) or up to 8 bytes (page write) are modified in one programming procedure. 5.1 byte write figure 7 byte write sequence the erase/write cycle is finished latest after 8 ms. acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3 acknowledge polling). address setting after a start condition the master transmits the chip select write byte csw. the eeprom acknowledges the csw byte during the ninth clock cycle. the following byte with the eeprom address (a0 to a6 or a7) is loaded into the address counter of the eeprom and acknowledged by the eeprom. transmission of data finally the master transmits the data byte which is also acknowledged by the eeprom into the internal buffer. programming cycle then the master applies a stop condition which starts the internal programming procedure. the data bytes are written in thememorylocationaddressedintheeeabyte(a0toa6or a7). the programming procedure consists of an internally timed erase/write cycle. in the first step, the selected byte is erased to 1. with the next internal step, the addressed byte is written according to the contents of the buffer. command byte csw s p c k a c k a s t a r t t p o s eeprom address eea data byte bus activity master sda line bus activity eeprom ied02129 c k a 0
slx 24c01/02 semiconductor group 12 1998-07-27 5.2 page write those bytes of the page that have not been addressed are not included in the programming. figure 8 page write sequence the erase/write cycle is finished latest after 8 ms. acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3 acknowledge polling). address setting thepagewriteprocedureisthesameasthebytewrite procedure up to the first data byte. in a page write instruction however, entry of the eeprom address byte eea is followed by a sequence of one to maximum eight data bytes with the new data to be programmed. these bytes are transferred to the internal page buffer of the eeprom. transmission of data the first entered data byte will be stored according to the eeprom address n given by eea (a0 to a6 or a7). the internal address counter is incremented automatically after the entered data byte has been acknowledged. the next data byte is then stored at the next higher eeprom address. eeprom addresses within the same page have common page address bits a2 through a6 or a7. only the respective three least significant address bits a0 through a2 are incremented, as all data bytes to be programmed simultaneously have to be within the same page. programming cycle the master stops data entry by applying a stop condition, which also starts the internally timed erase/write cycle. in the first step, all selected bytes are erased to 1. with the next internal step, the addressed bytes are written according to the contents of the page buffer. command byte csw s p c k a s t a r t t p o s eeprom address eea n data byte n data byte n+1 data byte n+7 bus activity master sda line bus activity eeprom ied02280 0 c k a c k a c k a c k a
slx 24c01/02 semiconductor group 13 1998-07-27 5.3 acknowledge polling during the erase/write cycle the eeprom will not respond to a new command byte until the internal write procedure is completed. at the end of active programming the chip returns to the standby mode and the last entered eeprom byte remains addressed by the address counter. to determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a start condition followed by a command byte csr or csw (read with b0 = 1 or write with b0 = 0). if the internal erase/ write cycle is not completed, the device will not acknowledge the transmission. if the internal erase/write cycle is completed, the device acknowledges the received command byte and the protocol activities can continue. figure 9 flow chart acknowledge polling internal programming procedure send start send cs-byte from eeprom acknowledge received? next operation no yes ied02131
slx 24c01/02 semiconductor group 14 1998-07-27 figure 10 principle of acknowledge polling csr s sda ied02166 1 p s 1 s csr s 1 p csr stop from master initiates erase/write cycle start from master acknowledge of eeprom indicates complete erase/ write cycle p s csw sda 0 s csw 0 s s 0 p csw e.g. stop condition stop from master initiates erase/write cycle start from master indicates complete erase/ acknowledge of eeprom write cycle
slx 24c01/02 semiconductor group 15 1998-07-27 6 read operations reading of the eeprom data is initiated by the master with the command byte csr. 6.1 random read random read operations allow the master to access any memory location. figure 11 random read address setting the master generates a start condition followed by the command byte csw. the receipt of the csw-byte is acknowledged by the eeprom with a low on the sda line. now the master transmits the eeprom address (eea) to the eeprom and the internal address counter is loaded with the desired address. transmission of csr after the acknowledge for the eeprom address is received, the master generates a start condition, which terminates the initiated write operation. then the master transmits the command byte csr for read, which is acknowledged by the eeprom. transmission of eeprom data during the next eight clock pulses the eeprom transmits the data byte and increments the internal address counter. stop condition from master during the following clock cycle the masters releases the bus and then transmits the stop condition. command byte csw s p a c k c k a s t a r t t p o s eeprom address eea n bus activity master sda line bus activity eeprom ied02133 c k a data byte 1 0 s t r a t s csr command byte
slx 24c01/02 semiconductor group 16 1998-07-27 6.2 current address read the eeprom content is read without setting an eeprom address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the master has served an interrupt). figure 12 current address read transmission of csr for a current address read the master generates a start condition, which is followed by the command byte csr (c hip s elect r ead). the receipt of the csr-byte is acknowledged by the eeprom with a low on the sda line. transmission of eeprom data during the next eight clock pulses the eeprom transmits the data byte and increments the internal address counter. stop condition from master during the following clock cycle the masters releases the bus and then transmits the stop condition. command byte csr s p a c k s t a r t t p o s bus activity master sda line bus activity eeprom ied02132 data byte 1
slx 24c01/02 semiconductor group 17 1998-07-27 6.3 sequential read a sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the eeprom. the eeprom then continues the data transmission. the internal address counter is incremented by one during each data byte transmission. a sequential read allows the entire memory to be read during one read operation. in the slx 24c02, after the highest addressable memory location is reached, the internal address pointer rolls over to the address 0 and the sequential read continues. in the slx 24c01, there is no roll over. the transmission is terminated by the master by releasing the sda line (no acknowledge) and generating a stop condition (see figure 13 ). figure 13 sequential read data byte n eeprom bus activity sda line master bus activity s r t a t s csw command byte 1 c k a c k a data byte n+x data byte n+1 a k c c k a p ied02134 s o p t
slx 24c01/02 semiconductor group 18 1998-07-27 7 electrical characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a =25 c and the given supply voltage. 7.1 absolute maximum ratings stresses above those listed here may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. parameter limit values units operating temperature range 1 (industrial) range 2 (automotive) C40to+85 C40to+125 c c storage temperature C 65 to + 150 c supply voltage C 0.3 to + 7.0 v all inputs and outputs with respect to ground C 0.3 to v cc +0.5 v esd protection (human body model) 4000 v 7.2 dc characteristics parameter symbol limit values units test condition min. typ. max. supply voltage v cc 4.5 5.5 v 5 v type v cc 2.7 5.5 v 3 v type supply current 1) (write) i cc 13 ma v cc =5v; f c = 100 khz standby current 2) i sb 50 m a inputs at v cc or v ss input leakage current i li 0.1 10 m a v in = v cc or v ss output leakage current i lo 0.1 10 m a v out = v cc or v ss input low voltage v il C0.3 0.3 v cc v
slx 24c01/02 semiconductor group 19 1998-07-27 1) the values for i cc are maximum peak values 2) valid over the whole temperature range 3) this parameter is characterized only input high voltage v ih 0.7 v cc v cc +0.5 v output low voltage v ol 0.4 v i ol =3ma; v cc =5v i ol =2.1ma; v cc =3v input/output capacitance (sda) c i/o 8 3) pf v in =0v; v cc =5v input capacitance (other pins) c in 6 3) pf v in =0v; v cc =5v capacitive load for each bus line c b 400 pf 7.2 dc characteristics (contd) parameter symbol limit values units test condition min. typ. max.
slx 24c01/02 semiconductor group 20 1998-07-27 1) theminimumriseandfalltimescanbecalculatedasfollows:20+(0.1/pf) c b [ns] example: c b = 100 pf ? t r =20+0.1 100 [ns] = 30 ns 7.3 ac characteristics parameter symbol limit values v cc = 2.7-5.5 v limit values v cc = 4.5-5.5 v units min. max. min. max. scl clock frequency f scl 100 400 khz clock pulse width low t low 4.7 1.2 m s clock pulse width high t high 4.0 0.6 m s sda and scl rise time t r 1000 1) 300 ns sda and scl fall time t f 300 1) 300 ns start set-up time t su.sta 4.7 0.6 m s start hold time t hd.sta 4.0 0.6 m s data in set-up time t su.dat 200 100 ns data in hold time t hd.dat 00 m s scl low to sda data out valid t aa 0.14.5 0.10.9 m s data out hold time t dh 100 50 ns stop set-up time t su.sto 4.0 0.6 m s time the bus must be free before a new transmission can start t buf 4.7 1.2 m s sda and scl spike suppression time at constant inputs t l 50 100 50 100 ns 7.4 erase and write characteristics parameter symbol limit values v cc = 2.7-5.5 v limit values v cc = 4.5-5.5 v units typ. max. typ. max. erase + write cycle (per page) t wr 58 58 ms erasepageprotectionbit 2.5 4 2.5 4 ms write page protection bit 2.5 4 2.5 4 ms
slx 24c01/02 semiconductor group 21 1998-07-27 figure 14 bus timing data t f r t hd.sta t su.sta t low t hd.dat t t su.dat t high t su.sto buf t dh t t aa ied02127 scl sda in sda out start condition stop condition
slx 24c01/02 semiconductor group 22 1998-07-27 8 package outlines sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. smd = surface mounted device dimensions in mm gpd05583 p-dip-8-4 (plastic dual in-line package) gps09032 p-dso-8-3 (plastic dual small outline package)

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